在20 nm FPGA中实现3.8ps均方根时间同步

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摘要翻译：
介绍了在20nm工艺ultrascale kintex现场可编程门阵列(FPGA)上实现的3.8ps均方根(RMS)时间同步。多通道高速串行收发器（如GTH）在量子密钥分发系统的光源等广泛应用中发挥着关键作用。然而，由于每个收发器中都存在独立的时钟分配器，因此每次系统上电或复位时，多个信道之间都会出现随机偏斜。Xilinx公司提供的自相位对准方法可以达到22 ps的均方根和100 ps的最大变化，远远不能满足2.5Gbps速率的应用要求。为了实现高精度的时间同步，提出了一种高精度时间数字转换器(TDC)和可调谐相位内插器(PI)相结合的协议。基于carry8基元的TDC用于测量40.7ps的槽内倾斜。每个GTH通道中嵌入的可调谐PI的理论步长为3.125ps。通过在最小步长内调整PI，最终的阵内时间同步精度达到3.8ps均方根，最大变化量为20ps，大大优于自相位对准方法。此外，通过闭环控制可以实现每个信道的期望时间偏移。
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英文标题：
《A 3.8 ps RMS time synchronization implemented in a 20 nm FPGA》
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作者：
Hong-Bo Xie, Yang Li, Qi Shen, Sheng-Kai Liao, Cheng-Zhi Peng
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最新提交年份：
2018
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分类信息：

一级分类：Electrical Engineering and Systems Science        电气工程与系统科学
二级分类：Signal Processing        信号处理
分类描述：Theory, algorithms, performance analysis and applications of signal and data analysis, including physical modeling, processing, detection and parameter estimation, learning, mining, retrieval, and information extraction. The term "signal" includes speech, audio, sonar, radar, geophysical, physiological, (bio-) medical, image, video, and multimodal natural and man-made signals, including communication signals and data. Topics of interest include: statistical signal processing, spectral estimation and system identification; filter design, adaptive filtering / stochastic learning; (compressive) sampling, sensing, and transform-domain methods including fast algorithms; signal processing for machine learning and machine learning for signal processing applications; in-network and graph signal processing; convex and nonconvex optimization methods for signal processing applications; radar, sonar, and sensor array beamforming and direction finding; communications signal processing; low power, multi-core and system-on-chip signal processing; sensing, communication, analysis and optimization for cyber-physical systems such as power grids and the Internet of Things.
信号和数据分析的理论、算法、性能分析和应用，包括物理建模、处理、检测和参数估计、学习、挖掘、检索和信息提取。“信号”一词包括语音、音频、声纳、雷达、地球物理、生理、（生物）医学、图像、视频和多模态自然和人为信号，包括通信信号和数据。感兴趣的主题包括：统计信号处理、谱估计和系统辨识；滤波器设计；自适应滤波/随机学习；（压缩）采样、传感和变换域方法，包括快速算法；用于机器学习的信号处理和用于信号处理应用的机器学习；网络与图形信号处理；信号处理中的凸和非凸优化方法；雷达、声纳和传感器阵列波束形成和测向；通信信号处理；低功耗、多核、片上系统信号处理；信息物理系统的传感、通信、分析和优化，如电网和物联网。
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英文摘要：
  A 3.8ps root mean square (RMS) time synchronization implemented in a 20nm fabrication process ultrascale kintex Field Programmable Gate Array (FPGA) is presented. The multichannel high-speed serial transceivers (e.g. GTH) play a key role in a wide range of applications, such as the optical source for quantum key distribution systems. However, owing to the independent clock dividers existed in each transceiver, the random skew would appear among the multiple channels every time the system powers up or resets. A self-phase alignment method provided by Xilinx Corporation could reach a precision with 22 ps RMS and 100 ps maximum variation, which is far from meeting the demand of applications with rate up to 2.5 Gbps. To implement a high-precision intrachannel time synchronization, a protocol combined of a high-precision time-to-digital converter (TDC) and a tunable phase interpolator (PI) is presented. The TDC based on the carry8 primitive is applied to measure the intrachannel skew with 40.7ps bin size. The embedded tunable PI in each GTH channel has a theoretical step size of 3.125 ps. By tuning the PI in the minimal step size, the final intrachannel time synchronization reaches a 3.8 ps RMS precision and maximal variation 20 ps, much better than the self-phase alignment method. Besides, a desirable time offset of every channel can be implemented with a closed-loop control.
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PDF链接：
https://arxiv.org/pdf/1806.034

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关键词：FPGA Applications Optimization distribution Application time 时间 相位 独立 TDC