·¢²¼Ê±¼ä£º2015-01-24 À´Ô´£ºÈË´ó¾­¼ÃÂÛ̳

ͨÐŹ¤³ÌרҵÂÛÎÄ Ä¿ ¼ 1ÒýÑÔ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­5 2»ùÓÚ³ËÀۼӽṹµÄFIRÊý×ÖÂ˲¨Æ÷¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­6 3»ùÓڶԳƲ¢ÐнṹµÄÁ÷Ë®ÏßËã·¨¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­7 3.1ʵÏÖFIRÂ˲¨Æ÷µÄÈýÖÖ·½°¸¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­7 3.1.1·Ö²¼Ê½Ëã·¨¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­7 3.1.2´®Ðз½Ê½¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­7 3.1.3²¢Ðз½Ê½¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­7 3.2FIRÂ˲¨Æ÷µÄ¾ßÌåʵÏÖ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­8 3.2.1±í´ïʽµÄÖ±½ÓÓÅ»¯¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­8 3.2.2¼Ó·¨Ê÷³Ë·¨Æ÷½á¹¹¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­8 3.2.3Á÷Ë®ÏßÓÅ»¯¼¼Êõ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­11 3.2.4×ÜÌå½á¹¹¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­11 4MatlabÉè¼ÆFIRÂ˲¨Æ÷¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­13 4.1´«Í³Éè¼Æ·½·¨¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­13 4.2MATLABÉè¼Æ·½·¨¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­13 4.2.1FDATool¼ò½é¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­13 4.2.2 Éè¼ÆÁ÷³Ì¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­14 5Ó²¼þµç·Éè¼Æ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­17 5.1ϵͳ¿òͼ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­17 5.2FPGA×îСϵͳ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­17 5.3ÍâΧµç·Éè¼Æ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­20 5.3.1Ðźŵ÷Àíµç·¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­20 5.3.2ADת»»µç·¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­24 5.3.3DAת»»µç·¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­25 5.3.4ÒôƵ·Å´óµç·¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­26 6Èí¼þÉè¼Æ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­ 28 6.1¿ª·¢Èí¼þºÍ±à³ÌÓïÑÔ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­28 6.2¿ª·¢Á÷³Ì¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­28 6.3Ö÷³ÌÐòÁ÷³Ìͼ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­29 6.4·ÂÕæ½á¹û¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­31 6.4.1´®²¢×ª»»¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­31 6.4.2·ÖƵÆ÷¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­31 6.4.3ADת»»¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­32 6.4.4¼Ó·¨Ê÷³Ë·¨Æ÷¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­33 6.4.5FIRÂ˲¨Æ÷¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­33 6.4.6²¢´®×ª»»¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­35 6.4.7DAת»»¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­36 6.4.8°´¼ü¼ì²â¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­37 7½áÊøÓï¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­39 ÖÂл¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­40 ²Î¿¼ÎÄÏס­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­41 ¸½Â¼¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­42 ¸½Â¼1²¿·ÖÖÐÓ¢ÎĶÔÕÕ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­42 ¸½Â¼2 Ô´´úÂëÇåµ¥¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­43 ¸½Â¼3Ó¢ÎÄÔ­ÎÄ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­55 ¸½Â¼4ÖÐÎÄÒëÎÄ¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­¡­65 ÕªÒª£ºÊý×ÖÂ˲¨ÊÇÓïÒôºÍͼÏó´¦Àí¡¢Ä£Ê½Ê¶±ð¡¢Æ×·ÖÎöµÈÓ¦ÓÃÖеÄÒ»¸ö»ù±¾´¦ÀíËã·¨,ÔÚÊý×ÖÐźŴ¦ÀíÖÐ, ËüÕ¼Óм«ÆäÖØÒªµÄµØλ. Õë¶Ô³£ÓõÄÈí¡¢Ó²¼þ·½·¨ÊµÏÖÓïÒôFIRÂ˲¨Æ÷´æÔÚµÄÎÊÌ⣬ÎÄÕÂÌá³öÁËÒ»ÖÖÔÚMATLABµÄFDA½çÃæÉÏÉè¼ÆFIRÊý×ÖÂ˲¨Æ÷µÄз½·¨ºÍ²ÉÓÃÏÖ³¡¿É±à³ÌÃÅÕóÁÐÆ÷¼þFPGA²¢ÐиßËÙʵÏÖÓïÒôÂ˲¨µÄÓ²¼þ½â¾ö·½°¸£¬²¢ÒÔÒ»¸ö16½×µÍͨFIRÊý×ÖÂ˲¨Æ÷µÄʵÏÖΪÀý˵Ã÷ÀûÓÃAltera¹«Ë¾CycloneϵÁÐоƬµÄÉè¼Æ¹ý³Ì¡£ÕâÖÖ·½°¸¿ÉÒÔ·½±ãµØµ÷ÕûÂ˲¨Æ÷µÄ½×ÊýºÍϵÊý£¬Êʺϲ»Í¬³¡ºÏµÄÓ¦Óá£ÎÄÕÂÌá³öµÄ¶Ô³Æ²¢ÐÐÁ÷Ë®½á¹¹¿ÉÒÔͬʱ¼æ¹ËFPGA×ۺϵÄËٶȺÍÃæ»ý£¬ÊµÏÖÁËFIRÂ˲¨Æ÷µÄÓ²¼þÓÅ»¯Éè¼Æ¡£ÓëÆäËûÀàÐ͵ÄÂ˲¨Æ÷Ïà±È£¬ÕâÖֽṹÀàÐ͵ÄÂ˲¨Æ÷ÔÚ×ÊÔ´ºÄÓá¢Â˲¨ËٶȺ͹¦ºÄµÈ·½Ãæ±íÏÖ³ö¸üÓÅÒìµÄÐÔÄÜ¡£·ÂÕæ±íÃ÷£¬ÔÚϵÊýÁ¿»¯Êý¾Ý¿í¶ÈΪ16λʱ£¬ÏµÍ³Ôڸߴï130MHzʱÖÓƵÂÊÏÂÄܹ»Îȶ¨¿É¿¿µØ¹¤×÷£¬¿ÉÒÔÂú×ãһЩ¸ß¾«¶Èʵʱ´¦Àíϵͳ¶Ô¾«¶ÈºÍËٶȵÄÒªÇó¡£ ¹Ø¼ü×Ö£ºFIRFPGA ÏßÐÔÏàλ ²¢ÐÐÁ÷Ë® Design of FIR Filter Running on FPGA Abstract: Digital filter is a basic settlement calculation method to speech sounds,image settlement,pattern discrimination and chart analysis.It plays a very important role in digital signal processing.Aiming at the problems in designing the audio FIR filter using software and hardware,a scheme is proposed which designs a FIR filter by the FDATool based on the MATLAB and runs it on FPGA parallelly with high speed.The article introduces the design process of a 16 order low-pass FIR digital filter using a Cyclone-chip provided by Altera company.The orders and coefficients of the filter may flexibly be adjusted to apply it in various applications.The connection between synthesis area restriction and speed restriction can be flexibly optimized through this improved FIR filter architecture arithmetic,which is symmetric, parallel and using pipelining technology.Compared with other FIR filters,this type performs better including resources sharing¡¢processing speed and power absorption.Through programming and simulating,it is shown that the system can work stably at the 130MHz frequency when the bits of coefficient quantization come to 16 ,proving the scheme is effective for designing high speed and real-time digital filter. Keywords: FIR FPGA linear phase parallel and pipelining