新型高速流水线数字电路的VLSI实现 无线接收机信号处理滤波器

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摘要翻译：
对具有高信噪比(SNR)的高性能收发器的需求驱动通信系统使用被识别为过采样系统的最新技术。它是通信系统中最经济的调制器和抽取器。它已经被证明可以提高信噪比，并被用于许多高性能系统，如无线收发器的模数转换器(ADC)。本文主要研究过采样技术中的一个子部件&抽取类的设计及其VLSI实现。并设计了抽取级的主要单元级联积分梳状滤波器(CIC)及其相关的半带滤波器和下垂校正的设计与实现。在Xilinx ISE环境下导出了Verilog HDL代码来描述所提出的高级CIC滤波器特性。最后，利用Virtex-II FPGA板在实际硬件上实现并测试了该设计。相应地进行了ASIC设计实现，完成了功率和面积测量的片上核心布局。本文的设计重点是在满足无线通信系统的芯片实现中，兼顾高速率与低功耗、硅面积与高分辨率之间的折衷。综合报告显示，最大时钟频率为332 MHz,有源核心面积为0.308×0.308mm2。因此，本文提出的滤波器结构的VLSI实现对于解决DSP应用中影响通信能力的问题具有重要意义。
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英文标题：
《VLSI Implementation of Novel Class of High Speed Pipelined Digital
  Signal Processing Filter for Wireless Receivers》
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作者：
Rozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman, Md Shabiul
  Islam, Mok Vee Hong
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最新提交年份：
2018
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分类信息：

一级分类：Electrical Engineering and Systems Science        电气工程与系统科学
二级分类：Signal Processing        信号处理
分类描述：Theory, algorithms, performance analysis and applications of signal and data analysis, including physical modeling, processing, detection and parameter estimation, learning, mining, retrieval, and information extraction. The term "signal" includes speech, audio, sonar, radar, geophysical, physiological, (bio-) medical, image, video, and multimodal natural and man-made signals, including communication signals and data. Topics of interest include: statistical signal processing, spectral estimation and system identification; filter design, adaptive filtering / stochastic learning; (compressive) sampling, sensing, and transform-domain methods including fast algorithms; signal processing for machine learning and machine learning for signal processing applications; in-network and graph signal processing; convex and nonconvex optimization methods for signal processing applications; radar, sonar, and sensor array beamforming and direction finding; communications signal processing; low power, multi-core and system-on-chip signal processing; sensing, communication, analysis and optimization for cyber-physical systems such as power grids and the Internet of Things.
信号和数据分析的理论、算法、性能分析和应用，包括物理建模、处理、检测和参数估计、学习、挖掘、检索和信息提取。“信号”一词包括语音、音频、声纳、雷达、地球物理、生理、（生物）医学、图像、视频和多模态自然和人为信号，包括通信信号和数据。感兴趣的主题包括：统计信号处理、谱估计和系统辨识；滤波器设计；自适应滤波/随机学习；（压缩）采样、传感和变换域方法，包括快速算法；用于机器学习的信号处理和用于信号处理应用的机器学习；网络与图形信号处理；信号处理中的凸和非凸优化方法；雷达、声纳和传感器阵列波束形成和测向；通信信号处理；低功耗、多核、片上系统信号处理；信息物理系统的传感、通信、分析和优化，如电网和物联网。
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一级分类：Computer Science        计算机科学
二级分类：Hardware Architecture        硬件体系结构
分类描述：Covers systems organization and hardware architecture. Roughly includes material in ACM Subject Classes C.0, C.1, and C.5.
涵盖系统组织和硬件架构。大致包括ACM主题课程C.0、C.1和C.5中的材料。
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英文摘要：
  The need for a high-performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize the latest technique identified as oversampling systems. It was the most economical modulator and decimation in the communication system. It has been proven to increase the SNR and is used in many high-performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and it's VLSI implementation which was the sub-component in the oversampling technique. The design and realization of the main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half-band filters, and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted in power and area measurement on-chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308 x 0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.
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PDF链接：
https://arxiv.org/pdf/1807.10309

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关键词：数字电路 信号处理 滤波器 接收机 LSI 核心 systems Digital filter area