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多路JTAG口下载器的设计_通信工程专业论文范文

发布时间:2015-01-24 来源:人大经济论坛
通信工程专业论文 以下为一级目录,详细目录及内容请与本站联系 目 录 引言………………………………………………………………………1 1 关于VHDL的介绍………………………………………………… 2 2 设计软件介绍……………………………………………………….5 3 硬件PCB电路板的制作…………………………………………….6 4 FPGA/CPLD技术及应用…………………………………………….10 5 CPLD/FPGA下载…………………………………………………… 13 6 设计方案……………………………………………………………19 7 结论…………………………………………………………………24 谢辞……………………………………………………………………25 参考文献………………………………………………………………26 附录1………………………………………………………………… 27 附录2………………………………………………………………… 29 摘 要 随着电子设计技术的飞速发展,专用集成电路ASIC和CPLD(Complex Programmable Logic Device)复杂可编程逻辑器件的复杂度越来越高,数字通信、工业自动化控制等领域所有的数字电路及系统的复杂程度也越来越高。我的毕业设计的题目是多路JTAG口下载器的设计,不仅要深入了解CPLD下载线的配置,而且要熟悉可编程逻辑芯片。 本文首先简要介绍了VHDL是VHSIC(Very High Speed Integrated Circuit) Hardware Description Language的缩写,是一门硬件描述语言,它的发展历程及其特点;以及MAX+PlusII软件系统的设计流程;硬件PCB电路板的制作;阐述了CPLD(Complex Programmable Logic Device)复杂可编程逻辑器件内部结构及发展,以及CPLD常规的设计流程和方法。在本文的核心部分详细说明了Byteblaster下载线的工作方式以及可编程逻辑芯片EPM7128。然后介绍我的设计原理及设计过程,利用MUXPLUS II对芯片进行自顶而下的设计,再用PROTEL进行硬件设计,将程序烧入芯片,使硬件工作。在本文最后是结论、谢辞等内容, 通过此次毕业设计,我受益非浅。 关键字:CPLD;VHDL;MAX PLUS2;Byteblaster下载线;EPM7128 Abstract Along with the rapid development of electronic design technology, special integrated circuit ASIC and CPLD (Complex Programmable Logic Device) need complexity higher. The digital circuit and the system complex degree of the digital communication, the industrial automation control and so on also need higher. The topic of my graduated paper is the multi-channel JTAG downloading device design. Not only I must understand the disposition of CPLD downloading line, but also I must be familiar with the programmable logic chip. The first part, a simple introduce of VHDL, which is a kind of hardware described language. In this part, I lead a basic view of VHDL and show how to use it to design the circuit. A simple introduction of MAXPLUS2 which is a software to modulate the program of the VHDL is the next one, and I also introduce how to design it. Next part is how to make hardware PCB electric circuit. I elaborate CPLD (Complex Programmable Logic Device) internal structure and the development, as well as CPLD convention design flow and method. In the fifth part, that is the main part of my paper. I write something about the work pattern of Byte blaster downloading line and the internal structure of programmable logic chip 7128. I also give my aim and process of design and introduce my principle of design. In the last part of my main paper, I write down a lot of my feelings and opinions which generated from the last three month, from my learning and experiment. That is the most important part of paper, as in the part I narrate many problems happened in my design and at last how I solved. From this graduation design, I have learnt a lot of actual knowledge, and studied many methods as well as how to think about tacking problems. I am very grateful for my classmates and teachers who have offered me much help. Key words: CPLD; VHDL; MAX PLUS2; Byte blaster downloading line; EPM7128
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